1. Field of the Invention
The invention relates to test devices for extremely high speed electronic devices and chips, and specifically to a mechanism for providing a high quality electronic interface between a tester device which operates at cryogenic temperatures and a device or chip under test which operates at a higher ambient temperature.
2. Description of the Prior Art
U.S. Pat. No. 4,401,900, Faris, Ultra High Resolution Josephson Sampling Technique, dated Aug. 30, 1983, shows time resolution of 5 picoseconds and sensitivity of 10 .mu.V. This was demonstrated experimentally using a cryogenic sampling system. The time resolution of this system is extendable to the sub-picosecond domain, limited ultimately by the intrinsic switching speed of the Josephson device used as the sampling gate. This can be as little as 0.09 picosecond in principle. This system is not restricted to measuring only fast waveforms produced in a cryogenic environment. Rather, it is extendable to general waveforms from various sources, such as X-rays or optical photons, if a suitable interface should be available.
It is also possible to measure electrical waveforms generated at room temperature, provided an adequate high performance interface scheme can be devised. In order to take advantage of the high resolution of 1 picosecond, the interface scheme has to satisfy the following constraints:
Frequency Constraint--A transmission line system for propagating the unknown signal from 300K to 4.2K with a 3 db cutoff frequency of 1000 GigaHertz is needed.
Transmission Line Length Constraint--The line has to be long enough, greater than about 3 cm, to allow for comfortable working space where the source of the unknown signal can be connected. The signal transmission line must pass through the outer dewar wall, through a vacuum region, through radiation shields, and through the inner dewar wall--and leave enough space for connecting the sampling chip which is immersed in liquid helium. Note that this constraint is in conflict with the frequency constraint which requires the length to be as short as possible.
Heat Loss Constraint--Heat loss, which is predominately caused by conduction through the high performance transmission line, must be minimized. This constraint is also in conflict with the frequency constraint. On the one hand, the line has to be short enough such that the attenuation is less than 3 dB at 1000 GigaHertz. On the other hand, we must maintain the smallest temperature gradient possible, which favors long lines. An optimum set of parameters exists which satisfies the above constraints.
Low Induction Constraint--In addition, picosecond resolution implies low inductance connections, on the order of 50 picohenries for a 50 ohm impedance system. This makes necessary the use of demountable connectors on the order of 100 .mu.m or less in length. This has been beyond the state of the art until now.
In attempting to deal with these stringent requirements, earlier workers in the field (Hamilton et al, IEEE Transactions on Magnetics, MAG-17, pp 577-582, 1981) chose to insert a chip inside a coaxial line to couple the signals therethrough to the devices on the chip where the signal is eventually measured. Their arrangement is constrained to have large coaxial lines having high thermal conductivity and in order to avoid heat losses, the lines are constrained to be long. In addition, this line arrangement cannot be adapted easily to planar chips. Furthermore, their system is constrained to couple only one line to a chip, which limits the system in utility.